When an integrated circuit is powered up, it is often critical that the circuit be set to a known state. Otherwise, if the circuit's state were some undefined, unexpected, or undesirable state, the resulting behavior could be incorrect. A power-on reset (POR) circuit is typically provided on such chips to provide resetting capability to the receiving circuit. The POR circuit generally includes some form of voltage detector monitoring the power supply (VCC) pin of the chip, so as to generate a reset signal under appropriate conditions.
A chip in production is normally tested to ensure that it functions correctly before it is delivered to a customer. In order to reduce testing time, the test equipment typically provides very fast rise and fall times to the pins of the chip, including the VCC pin. Under these testing conditions, the voltage detector will naturally generate a reset signal on power-up, so that the receiving circuit of the chip under test will be reset to a known state. The circuit operation will test correctly and receive a pass/fail result based on its subsequent behavior during the test.
However, VCC rise or fall characteristics at the customer end are generally unpredictable, even if constrained somewhat by parameter requirements published in product data sheets. In any case, normal VCC rise and fall times are generally slower than the test conditions. Moreover, the voltages of a power supply signal in a test typically range from full off (OV) to full on (a nominal high voltage level VH), which may differ somewhat from a customer's normal operating environment or in abnormal or unusual circumstances. Thus, we need a way to test the on-chip POR circuit itself, and not just the receiving circuit, in order to ensure that a reset will occur under any of the VCC power supply conditions that can be expected to occur in a user environment. It may be necessary to better characterize the reset trip point and identify voltage conditions of the chip under test when a reset might fail to occur or might improperly occur.
U.S. Pat. No. 5,450,417 to Truong et al. describes an on-chip test circuit for testing the power-on reset circuitry in integrated circuits. In particular, the test circuit includes a pair of latches to detect the occurrence of a power-on reset signal pulse.
U.S. Patent Application Publication No. 2006/0041811 to Hsieh describes a circuit comprising two variable resistors and a jumper with four pins, all disposed on a test board, for testing the power down reset function of an electronic device.